The present invention relates to image processing systems and methods, and more particularly to digital systems and methods.
A wide variety of image processing systems have been developed enabling digital computers to "see" or "read" an image. Typically, these image processors include a video camera, an analog-to-digital converter for digitizing the video signal produced by the camera, and a digital device for processing the digitized information. Typically, the image is digitized into a matrix or lattice of pixels with each video scan line divided into 512 pixels. These image processors are capable of scanning digital images and processing the digital information to interpret the image.
One extremely efficient image processor is disclosed in U.S. patent application Ser. No. 513,448, filed July 13, 1983, by Sternberg, entitled APPARATUS AND METHOD FOR IMPLEMENTING DILATION AND EROSION TRANSFORMATIONS IN DIGITAL IMAGE PROCESSING, and assigned to the assignee of the present application. The system disclosed therein includes digital circuitry for effecting a dilation of a serialized digital stream representative of an image. More specifically, the circuitry includes digital devices for repetitively delaying the serialized digital signal and ORing the delayed digital signal back into the serialized signal stream.
In further development of the Sternberg image processor, it was recognized that the device had two limitations. First, the processor performed its signal processing by repetitively delaying the serial signal and ORing the delayed signal back into the cumulative signal stream. Consequently, the processor is capable of dilating and/or eroding by a restricted variety of structuring elements (i.e., polar symmetric structuring elements). Second, the delays for the digital signal streams were either shift registers or rings implemented in random access memory. Shift registers for relatively long delays were relatively complicated and expensive when implemented in hardware. On the other hand, reading and writing the data stream pixel-by-pixel into and out of a random access memory at the requisite rate of 10 megahertz required extremely fast and expensive memory devices.
Another image processor, less efficient than the above described Sternberg device, routes the image sequentially through several neighborhood transformations to detect limited image features. At each neighborhood transformation stage, the "neighborhood" of pixels surrounding a given pixel in one image is examined and the corresponding pixel in the new image is given a digital value which is a function of the neighborhood pixels in the old image. All neighborhood pixels in an image are made available for processing by serially routing the digital image through one or more shift registers. As the image is shifted through the registers, the appropriate register locations are simultaneously accessed to process a particular neighborhood.
The neighborhood processor is not without its drawbacks. First, the entire neighborhood of a pixel must be made available and examined before the corresponding pixel in the new image can be given a value. This requires delay and excessively complicated circuity to make the neighborhood pixels simultaneously available to drive the neighborhood function generator. Second, the neighborhood processing theory is an inefficient and cumbersome method of effecting image transformations. Third, the neighborhood theory greatly restricts the operations which can be performed, due to the limited size of the neighborhood. Although in theory the neighborhood could be enlarged, the hardware required to implement such a neighborhood enlargement would be relatively expensive and/or complicated.